Defense Semiconductor IP
A company that assembles finished drives and a company that designs the silicon inside them are not the same thing. PaxDisk designs and owns its semiconductor IP — from the controller, the interface and error correction through to security, a processor core and DSP — and builds its defense products on top of it.
Localization timeline
Controller → interface → error correction
Localising storage silicon happens in a fixed order. PaxDisk has cleared all three stages.
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2012
World's first 2TB SSD — in-house SSD controller
PaxDisk announced the world's first 2TB SSD, built on its own SSD controller. The same year it signed an SSD patent agreement with SK hynix.
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2013
Domestic SATA 6Gbps Link / Transport IP
PaxDisk developed a domestic SATA 6Gbps Link/Transport semiconductor IP — the point at which the physical interface layer of the storage device came under Korean technology.
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2026
156-bit BCH ECC (t=156)
PaxDisk completed a world-class BCH ECC engine usable on process nodes down to 2nm. After the controller and the interface, error correction too is now covered by domestic IP.
IP catalogue
IP portfolio
The portfolio spans controller, interface, error correction, security, processor and DSP. Headline specifications only — full datasheets, manuals and integration guides are available on request.
11 cores · 6 families
Controller
SSD Controller
1.44MB to 16TB from a single controller
The controller lineage that drove the world's first 2TB SSD in 2012. Because we own the design down to the interface layer, we can answer obsolescence and tailor a build to your requirement.
Headline specs · block diagram · full description →
Interface IP
SATA 6Gbps Link / Transport
Domestic SATA Gen3 interface IP
The SATA Gen3 Link/Transport core developed in Korea in 2013. It is why we can stand behind the performance and compatibility of the finished drive with our own engineering.
Headline specs · block diagram · full description →
Interface IP
UFS Host Controller (AXI4)
A JEDEC UFSHCI 3.0 host controller in pure RTL
After SATA, the current storage interface is in-house IP as well. It is the host controller that turns driver-written descriptors into link transactions between the SoC bus and a UFS device, implementing the transport, UniPro and data-link layers entirely in RTL.
Headline specs · block diagram · full description →
ECC
156-bit BCH ECC
Parametric BCH codec, t = 8 … 156
ECC is the last line of defence in SSD reliability. This encoder/decoder pair takes correction strength and sector size as build-time parameters and drops into a controller as synthesisable RTL.
Headline specs · block diagram · full description →
ECC
QC-LDPC Error Correction
Soft-decision error correction for 3D NAND TLC / QLC
High-density NAND storing more bits per cell needs soft-decision correction. An inner QC-LDPC code is concatenated with an outer BCH code and CRC32 to drive the residual failure rate down.
Headline specs · block diagram · full description →
Security IP
PBKDF2-HMAC Key Derivation
Password to key — an RFC 8018 hardware engine
A self-encrypting drive starts with turning a password into a key safely. This engine performs the key stretching — repeated HMAC rounds that raise the cost of a brute-force attack — entirely in hardware, with no software in the path.
Headline specs · block diagram · full description →
Security IP
AES-128/256 Encryption
Combined encrypt/decrypt engine with DMA streaming
The AES engine that encrypts the data behind the key-derivation stage. A single core covers key expansion, encryption and decryption, and supports both register-driven single-block operation and continuous DMA streaming. It is designed to sit in an SSD controller datapath.
Headline specs · block diagram · full description →
Processor IP
RV32IMAC RISC-V Core
A domestic 32-bit RISC-V soft processor
The processor that runs the firmware inside the controller is now in-house IP as well. It is a soft processor implementing the open RISC-V instruction set (RV32IMAC), feeding instructions and data from 128 KB of on-chip memory in one cycle each.
Headline specs · block diagram · full description →
DSP IP
ADSP-2181 Compatible DSP Core
Replaces an obsolete DSP, running its original binaries
A platform stays in service for twenty years; the DSP inside it goes out of production long before that. This core implements the genuine 24-bit ADSP-21xx instruction encoding, so binaries from the original toolchain run unmodified — no source port, no re-qualification of the algorithm.
Headline specs · block diagram · full description →
DSP IP
DSP56001 Compatible DSP Core
A 24-bit fixed-point DSP — in active development
A 24-bit fixed-point core targeting Motorola DSP56001 compatibility. Rather than claim completion we publish the verification level as it stands: the instruction encoding is cross-checked against official assembler listings, and the core datapath executes real DSP kernels.
Headline specs · block diagram · full description →
DSP IP
TMS320C54x Compatible DSP Core
16-bit fixed-point DSP — single-cycle MAC, Viterbi acceleration
A 16-bit fixed-point DSP core, instruction-level compatible with the TI TMS320C54x. On an architecture that separates one program bus from three data buses, a 17x17 multiplier and a dedicated 40-bit adder perform a single-cycle MAC, and a compare-select-store unit accelerates the Viterbi operation.
Headline specs · block diagram · full description →
Engagement model
From a licence to joint development
From licensing a verified core as it stands through to joint development against a platform requirement — start wherever you need to. Scope and terms are agreed case by case.
- 01 IP licence — Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.
- 02 Custom development — The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.
- 03 Co-development & national programmes — Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.
01
IP licence
Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.
02
Custom development
The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.
03
Co-development & national programmes
Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.
What a licence includes
- Synthesisable Verilog RTL and integration wrappers
- Cycle-accurate reference model and equivalence checker
- Full-chain testbench (clean / correct / UE / pad vectors)
- Datasheet, manual and integration guide (on request)
Verification toolchains
Intel/Altera (Quartus)AMD/Xilinx (Vivado)ASIC — process-portable RTL
The RTL is process-portable, so the same source carries from FPGA prototype through to ASIC production.
Why a defense programme picks us
What domestic IP means for a defense programme
Domestic IP — free of export control
From the controller, interface and error correction through to security, the processor core and DSP — designed and owned in Korea. Your programme schedule is not hostage to a foreign vendor’s licensing policy or an export-control review.
Support across the life cycle
Defense platforms live in decades. The company that has kept shipping obsolete interfaces since the 2005 PATA SSD applies the same standard to IP support.
Twenty years of defense delivery
We are not a design house that only sells IP. Products built on this IP are fielded on the K2, Cheongung-II, Surion and K-21 — the qualification path already exists.
IP Licensing
IP licensing & co-development enquiries
Tell us the target process, the correction strength you need, the interface requirement and an outline schedule — an engineer replies directly. Detailed specifications and datasheets are available on request.
These design assets become products — See the defense SSD line-up → · See the track record →